1. Field of the Invention
The invention relates to a method for fabricating a CMOS device, more particularly to a method for fabricating a CMOS device in which the number of photolithography steps involved during the formation of NMOS and PMOS transistors is minimized.
2. Description of the Related Art
A conventional method for fabricating a CMOS device is described as follows:
Referring to FIG. 1, an intermediate semiconductor device 1 is prepared according to the process steps of the flowchart shown in FIG. 2. Initially, P-type and N-type impurities are implanted into a substrate 10 to form P-type wells 11 for NMOSFETS and N-type wells 12 for PMOSFETS. A silicon nitride layer (not shown) is then deposited over surfaces of the NMOS and PMOS transistor wells 11, 12, and the silicon nitride layer is etched to expose isolation regions around the NMOS and PMOS transistor wells 11, 12. Field oxide layers 13 are then grown on the isolation regions. The silicon nitride layer is removed, and a threshold adjust implant step is performed in order to adjust the threshold voltages of the NMOS and PMOS transistors that are to be formed. A gate oxide layer 14 which overlies the surfaces of the NMOS and PMOS transistor wells 11, 12 is grown, and a polysilicon layer is then deposited on the gate oxide layer 14. The polysilicon layer is etched to form gate electrodes 15, 16 for the NMOS and PMOS transistors. Finally, a first screening oxide 17 is grown and envelops the gate electrodes 15, 16. The intermediate semiconductor device 1 is now ready for source/drain ion implantation.
During the source/drain ion implantation procedure, the surface of the intermediate semiconductor device 1 is coated with a first photoresist layer 18, as shown in FIG. 3. The portion of the first photoresist layer 18 above the NMOS transistor well 11 is patterned through exposure and development, as shown in FIG. 4, and the NMOS transistor well 11 is subjected to N-LDD ion implantation with the patterned first photoresist layer, the polysilicon gate electrode and the field oxide layer as masks, as shown in FIG. 5.
The remaining portion of the first photoresist layer 18 is removed, as shown in FIG. 6, and a second photoresist layer 19 is coated on the surfaces of the NMOS and PMOS transistor wells 11, 12, as shown in FIG. 7. The portion of the second photoresist layer 19 above the PMOS transistor well 12 is patterned through exposure and development, and the PMOS transistor well 12 is subjected to P-LDD ion implantation with the patterned second photoresist layer, the polysilicon gate electrode and the field oxide layer as masks.
Thereafter, the remaining portion of the second photoresist layer 19 is removed, as shown in FIG. 8. A thin layer of oxide is deposited on the surface and is then subjected to an etch-back process to form a sidewall spacer 20 on each side of the gate electrodes 15, 16, as shown in FIG. 9. A second screening oxide 201 is then deposited over the NMOS and PMOS transistor wells 11, 12.
A third photoresist layer 21 is coated on the surfaces of the NMOS and PMOS transistor wells 11, 12, as shown in FIG. 10. The portion of the third photoresist layer 21 above the NMOS transistor well 11 is patterned through exposure and development, and the NMOS transistor well 11 is subjected to N+ ion implantation to form the NMOS source and drain 22 with the patterned third photoresist layer, the polysilicon gate electrode, the sidewall spacer and the field oxide layer as masks.
Next, the remaining portion of the third photoresist layer 21 is removed, as shown in FIG. 11, and a fourth photoresist layer 23 is coated on the surfaces of the NMOS and PMOS transistor wells 11, 12, as shown in FIG. 12. The portion of the fourth photoresist layer 23 above the PMOS transistor well 12 is patterned through exposure and development, and the PMOS transistor well 12 is subjected to P+ ion implantation to form the PMOS source and drain 24 with the patterned fourth photoresist layer, the polysilicon gate electrode, the sidewall spacer and the field oxide layer as masks. Finally, the remaining portion of the fourth photoresist layer 23 is removed, as shown in FIG. 13, thereby completing the source/drain ion implantation procedure of the conventional CMOS fabricating method.
In the fabrication of integrated circuits, the stepper equipment for performing photolithography is considered to be among the most expensive. It is noted that there are four photolithography steps involved in the source/drain ion implantation procedure of the conventional method for fabricating a CMOS device. If the number of photolithography steps in the method for fabricating a CMOS device can be reduced, the number of stepper equipments required in the mass production of CMOS devices can be correspondingly reduced to result in a reduction in the manufacturing cost of the CMOS device.